1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method of planarizing (flattening) a rough surface of a semiconductor substrate by filling depressed (concave or trench) portions on the semiconductor surface with a burying material.
2. Description of the Prior Art
In manufacturing highly integrated semiconductor devices such as VLSI devices, it is necessary to reduce the level difference produced on the surface of a semiconductor substrate. In the case of multi-layer interconnection techniques, for instance, when an interlayer insulating film is deposited on a first metallic interconnection layer and further a second metallic interconnection layer is formed on the interlayer insulating film, since a level difference is inevitably produced in the second metallic interconnection layer, there exists a problem in that the reliability is degraded due to disconnection or an increase of resistance. Accordingly, it is necessary to planarize the interlayer insulating film deposited between the two metallic interconnection layers.
Further, when trenches are formed on the surface of a semiconductor substrate as element isolation regions or capacitances, as with the case of DRAM devices, it is also necessary to bury trenches (depressed portions) in the same way as above.
A conventional method of planarizing the surface of a semiconductor substrate by burying concave portions on the semiconductor substrate surface will be described hereinbelow with reference to the attached drawings.
FIG. 10 is a cross-sectional view for assistance in explaining a conventional planarizing method. In FIG. 10, there are convex portions 10B and concave portions 104 on the surface of a semiconductor substrate 101. Therefore, a burying material is deposited all over the surface of the semiconductor substrate 101 to form a burying film 102 and to bury the concave portions 104. Thereafter, the substrate 101 is polished flatwise to the surface of the convex portions 103 from above as shown by dashed lines in FIG. 10, so that only the concave portions 104 can be filled with a burying film 102 for planarization of the surface of the semiconductor substrate 101.
In this conventional method, however, when the area of the concave portion is large, since the surface is depressed, the degree of surface planarization has been not so far satisfactory as a whole.
To overcome the above-mentioned problem, another method has been proposed. This conventional method will be described hereinbelow with reference to FIG. 11A to 11G, in which the similar portions are designated by the same reference numerals shown in FIG. 10.
In this method, as shown in FIG. 11A, a stopper layer 201 having a low mechanical polishing speed is formed on the surfaces of the convex portions 103 on the surface of the semiconductor surface 101. Thereafter, as shown in FIG. 11B, a burying film 102 is formed by depositing a burying material all over the surface of the semiconductor substrate 101. Under these conditions, the burying film 102 is depressed as a concave portion 105 at a relatively broad convex portion 104. Further, as shown in FIG. 11C, a planarizing block (resist) 202 is selectively formed at the concave portion 105 of the burying film 102. Further, as shown in FIG. 11D, a planarizing material of high fluidity is applied on the convex and concave portions 103 and 104 and dried to form a planarizing film 203. Thereafter, as shown in FIG. 11E, the planarizing film 203, the planarizing block 202 and a burying film 102 are all etched back by reactive ion etching (RIE), which is an anisotropic etching to the vicinity of the stopper layer 201. Finally, as shown in FIG. 11F, a rough portion 204 produced due to a difference in the etching speed of the RIE between the respective materials is removed by mechanical polishing. In this process, the end of the mechanical polishing can be controlled by the presence of the stopper layer 201.
In the above-mentioned mechanical polishing method (referred to as polishing method or lapping method), a surface grinder is rotated under the condition that the grinder surface is brought into tight contact with the surface of the semiconductor substrate. In this polishing, an appropriate abrasive material for cutting off the material of the substrate surface is intervened between the surface grinder and the substrate surface to cut off the material of the substrate surface. The abrasive material is a liquid including uniform spherical particles of silicon oxide with particle diameters of about several tenths of a micron to several microns and a liquid including these particles separately without gelatinization.
Further, as shown in FIG. 11G, when the stopper layer 201 is removed, it is possible to obtain a semiconductor structure in which the concave portions 104 of the semiconductor substrate are filled with a burying film 102 being flush with the surface layer of the convex portions 103 of the semiconductor substrate 101.
In the conventional method, however, since the planarizing block 202 and the two planarizing layers 102 and 203 are required to be formed, there exists a problem in that the number of manufacturing processes increases. In addition, the RIE etching rates of the planarizing block, the planarizing layers and the burying material must be all equal to each other in order to increase the degree of planarization. In practice, however, it is very difficult to select such materials and such manufacturing conditions that the RIE etching rates for these three layers become equal to one another, with the result that the finally remaining convex and concave portions must be further polished mechanically. In other words, two processes of the RIE and the mechanical polishing are inevitably required for the conventional planarization process, thus raising a problem in that the number of manufacturing processes is increased.
Further, it is also possible to planarize the substrate surface by effecting the mechanical polishing together after the planarizing block and the planarizing layer have both been formed. In this method, however, since the mechanical polishing speed must be increased to increase the productivity thereof, the roughness of the polished substrate surface increases with increasing polishing speed and in addition it is rather difficult to control the mechanical polishing by the presence of the stopper layer. Further, in this method, although the mechanical polishing speed must be kept uniform for the three layers from the standpoint of planarization, in the same way as with the case of the RIE, this is more difficult than the case of the RIE. Further, in order to shorten the polishing time, in the case where the substrate is polished without forming the planarizing block 202 or the planarizing layer 208, although the polishing speed at the concave portions is slow as compared with that at the convex portions, since the polishing speeds at both the portions become close to each other at the middle portion in a broad concave portion, the burying material is polished away at only the concave portions, with the result that it is difficult to planarize all over the surface of the semiconductor substrate.